Recently, an ultra-high-speed optical communication standard, such as OC-192 (10 Gbps) or OC-768 (40 Gbps) has obtained general acceptance in communication equipment, such as a switch or a router. As an SRAM (static random access memory) technique for implementing the data transfer rate complying with these standards, QDR (Quad Data Rate)/DDR (Double Data Rate) has been jointly developed. For example, QDRII/DDRII SRAM is of the specifications supporting the maximum operating frequency up to 333 MHz (NEC Press Release: Apr. 15, 2002-2: “http://www.nec.co.jo/press/ja/0204/1502/html”). In the QDRII architecture, a data port is divided into an input port and an output port (I/O separation), these ports each operating at a double rate. Meanwhile, QDR is a registered trademark owned by IDT Inc. and Micron Inc.
In the DDR, a read cycle of reading data from a memory cell array and a write cycle of writing data in the memory cell array occur in alternation with each other.
Referring to FIG. 2, the outline of the QDR type memory device is described. Meanwhile, FIG. 2 is a diagram which is referred in the detailed description of the embodiment of the present invention. In FIG. 2, there are provided a plural number of memory cell array blocks 10 of the same structure. In FIG. 2, the structure of one memory cell array block 10 is shown. The cell array block 10 includes a cell array 100, an X selection circuit 101 which comprises an X-decoder for decoding X addresses, a word driver driving a word line selected as a result of decoding by the X-decoder, circuits 103 which comprises a Y selection circuit having a Y decoder for decoding a Y address, a Y switch connecting the bit line of the column selected as a result of decoding by the Y decoder to a sense amplifier or to a write amplifier, a sense amplifier SA and a write amplifier WA, and a control circuit 102.
An input register 109, which composes an input port, samples write data from an input terminal Din, in synchronism with a clock signal CLK, and sends the sampled write data over a write bus to the write amplifier WA. An output register 108, having an input terminal connected to a read bus, to which data from the sense amplifier SA is output, samples read data (read data) in synchronism with the clock signal CLK, to output the sampled data at an output terminal Dout.
A read pulse generator 106 receives a read/write (R/W) command and outputs a read control pulse RPB during the read (read) operation to a control circuit 102.
A write pulse generator 107 receives a read/write command and outputs a write control pulse WPB during the write operation to the control circuit 102.
An address clock generator 105 receives a read/write command and generates and outputs a read clock RC and a write clock WC at a transition edge of the clock signal CLK.
An address register 104 receives an address signal Add from a memory controller or a chip set and samples the address signal with the rising edge of the clock signal CLK. When the read clock RC or the write clock WC are activated, the address register 104 outputs the sampled address (X-address, Y-address and block selection address). The X-address, Y-address and the block selection address are supplied to the X-decoder, Y-decoder and to for example the control circuit 102, respectively. The control circuit 102 receives a read control pulse RPB and a write control pulse WPB and generates a read activation signal and a write activation signal used in the memory array block 10 to control the activation of the selected word line, the sense amplifier SA and the write amplifier WA.
As described above, the memory device includes plural cell array blocks 10, thus elongating the bus length of the read bus and the write bus or the length of the signal interconnection for control signals for the read controlling pulses RPB and the write controlling pulses WPB. As the operating frequency of the memory device is increased, that is, the clock period is shortened, the skew between the far and near ends of the signal interconnection has become marked and cannot be disregarded. The increase of the memory capacity brings about an increased bit width of address signals and an increased number of stages of the circuits making up the decoder, such as X-decoder, while also the skew of change points of an inner address signal supplied to the cell array as a result of address decoding becomes marked.
In the design specification of for e.g. QDR, read and write cycles occur alternately. In this case, the cycle time is determined taking the skew of control signals, such as RPB or WPB, and an inner address signal into account.